1. Field of the Invention
The present invention relates to a switching regulator and a method of converting a DC voltage.
2. Description of Related Art
A DC-DC converter is a converter circuit for generating a required DC voltage from a given DC voltage, and also referred to as a switching power supply or a switching regulator. A feature of this circuit is to utilize a ratio in time between ON and OFF states of a switch and charge/discharge phenomena of an inductor L and a capacitor C to be able to obtain a desired voltage. While in order to obtain the desired voltage, another power supply circuit converts unnecessary energy into heat to remove it through a resistor, the DC-DC converter segments a power supply voltage by ON/OFF switching of the switch, and utilizes the charge/discharge of the inductor and the capacitor to be able to supply just necessary energy to a load. That is, the DC-DC converter can obtain the desired voltage theoretically without losing energy, and therefore has a feature of higher efficiency (power efficiency) as compared with the other power supply circuit. Note that the efficiency herein is represented by a relationship of a following expression, where the output voltage is a voltage supplied from the DC-DC converter to a load circuit; a load current is a current flowing into the load circuit depending on the output voltage; an input voltage is a power supply voltage converted by the DC-DC converter; and an input current is a current input to the DC-DC converter depending on the input voltage:Efficiency=((Output voltage×Load current) /(Input voltage×Input current))×100[%]
Referring to FIGS. 1 to 3, a circuit configuration and an operating principle of a. synchronous rectification type DC-DC converter is described, which is widely known as one type of the DC-DC converters. FIG. 1 is a circuit diagram illustrating a basic circuit configuration of a step-down type synchronous rectification DC-DC converter. The step-down type synchronous rectification DC-DC converter (hereinafter referred to as a switching regulator 100) includes a reference voltage generating circuit 110, an error voltage amplifying circuit 120, a pulse generating circuit 130, an inverter circuit 150 and a filter circuit 200 The reference voltage generating circuit 110 (e.g., a voltage generating circuit including a regulator), the error voltage amplifying circuit 120, the pulse generating circuit 130 and the inverter circuit 150 are provided on one IC (Integrated Circuit) chip, and connected to a load circuit 300 through the filter circuit 200 formed outside the IC chip.
The inverter circuit 150 includes: a P-channel power MOS transistor P10 (MOS: Metal Oxide Semiconductor) (hereinafter referred to as a PMOS transistor P10); and an N-channel MOS transistor N10 (hereinafter referred to as a NMOS transistor N10), both for switching a power supply voltage VDD to output a pulse voltage. The filter circuit 200 includes an inductor and a capacitor both for smoothing the pulse voltage output from the inverter circuit 150. The error voltage amplifying circuit 120 includes: resistors R1 and R2 for dividing a value of the smoothed output voltage Vout; a buffer Amp1 for feeding back a voltage divided by the resistors to the switching regulator 100; and an error amplifier Amp2 for amplifying a difference between a reference voltage supplied from the reference voltage generating circuit 110 and the voltage into which the output voltage Vout is divided by the resistors Note that the error amplifier Amp2 is connected with resistors R3 and R4 operating as attenuators. An output from the buffer Amp1 is supplied to the error amplifier Amp2 through the resistor R3. An output signal 91 of the error amplifier Amp2 is fed back to itself through a capacitor C1 and the resistor R4 connected in parallel to each other, as well as being supplied to the pulse generating circuit 130. The pulse generating circuit 130 includes: an oscillation circuit 131 for outputting an output signal 92 for determining a switching period of the inverter circuit 150; a comparator 132 for comparing the output signal 91 of the error amplifier Amp2 and the output signal 92 of the oscillation circuit 131 with each other; and a timing adjustment circuit 133 for adjusting timing of an output (pulse signal) from the comparator 132 to output it to the inverter circuit 150 as pulse signals 93 and 94.
Now, referring also to FIG. 2, operations of the switching regulator 100 are described. The timing adjustment circuit 133 adjusts signal levels of the pulse signals 93 and 94 to be output to the inverter circuit 150, according to a result of the comparison between the output signal 91 dependent on the output voltage Vout and the output signal 92 from the oscillation circuit 131. For example, referring to FIG. 2, if a voltage value of the output signal 92 is larger than that of the output signal 91, a signal level of the pulse signal 93 is brought to a Low level. At this time, the PMOS transistor P10 is turned ON. On the other hand, if the voltage value of the output signal 92 is smaller than that of the output signal 91, the signal level of the pulse signal 93 is brought to a High level. At this time, the PMOS transistor P10 is turned OFF. In this manner, the timing adjustment circuit 133 changes the signal level of the pulse signal 93 according to a period of the output signal 92 to control ON/OFF (switching) of the PMOS transistor P10. Similarly, the timing adjustment circuit 133 changes a signal level of the pulse signal 94 according to the period of the output signal 92 to control ON/OFF (switching) of the NMOS transistor N10. Note that if a value of the output voltage Vout increases, the voltage value of the output signal 91 is increased, so that an ON time of the PMOS transistor P10 becomes shorter, whereas an ON time of the NMOS transistor N10 becomes longer. On the other hand, if the value of the output voltage Vout decreases, a similar feedback is performed such that a ratio in time of the switching (ratio in ON/OFF time between the PMOS transistor P10 and the NMOS transistor N10) is changed in the opposite direction.
Note that if there is no timing adjustment circuit 133 and therefore the output of the comparator 132 is output to the inverter circuit 150 without change, a time period for which the PMOS transistor P10 and the NMOS transistor N10 are simultaneously in the ON states arises, and a through current flows during the time period. The through current is s a significant factor causing a reduction in efficiency upon driving of the switching regulator 100. For this reason, it is effective to provide the timing adjustment circuit 133 between the output of the comparator 132 and the inverter circuit 150. As shown in FIG. 2, the timing adjustment circuit 133 finely adjusts pulse widths such that the PMOS transistor P10 and the NMOS transistor N10 are not simultaneously brought into the ON states.
Meanwhile, one of the factors affecting the efficiency of the switching regulator 100 lies in MOS sizes (ON resistances) of the PMOS transistor P10 and the NMOS transistor N10 in the inverter circuit 150. The MOS sizes and ON resistances of the PMOS transistor P10 and the NMOS transistor N10 in the inverter circuit 150 are hereinafter simply referred to as MOS sizes and ON resistances. The inverter circuit 150 has heat loss due to a load current Il flowing through the load circuit and a transient loss due to parasitic capacitance, and therefore the appropriate MOS sizes exhibit different values depending on an operating condition. For this reason, the efficiency in a case where the load current Il is changed under a condition of the output voltage Vout being constant is, as illustrated in FIG. 3, changed so as to draw a load curve 70 having a peak (optimum efficiency ηD). For example, if the MOS sizes are designed to achieve the optimum value (efficiency ηD) at a load current Ides, connecting the load circuit 300 causing the load current Il different from the load current Ides to the switching regulator results in a reduction in the efficiency. This is because a load current different from the optimum load current Ides causes the reduction in the efficiency due to the ON resistances and parasitic capacitance in the inverter circuit 150. For example, if the load current Il is Iuse1 smaller than the load current Ides, the efficiency is reduced depending on switching loss, resulting in a value lower than the efficiency ηD by E1. On the other hand, if the load current Il is Iuse2 larger than the load current Ides, the efficiency is reduced depending on the ON resistances, resulting in a value lower than the efficiency ηD by E2.
For these reasons, in order to drive the switching regulator at a peak (maximum value) of the efficiency curve, it is important to set the MOS sizes (ON resistances) optimized for every use condition such as the load current Il or the output voltage Vout.
The switching regulator is widely used for portable devices such as battery-driven digital cameras and cellular phones, and devices requiring low power consumption. For this reason, the switching regulator having a high efficiency to extend an operating time as much as possible is required. Control of the ON resistance (MOS size) dominating the efficiency is an important element for driving the switching regulator at the peak of the efficiency curve. Japanese Patent No. 3438330 describes a power supply apparatus (DC-DC converter) in which an ON resistance of a transistor is controlled to improve efficiency.
The power supply apparatus described in Japanese Patent No. 3438330 includes: a plurality of parallely connected switch elements (equivalent to the PMOS transistor P10 or the NMOS transistor N10 in FIG. 1) for generating a pulse signal depending on an output voltage; and a switch element selection circuit for selecting from the plurality of switch elements one to which the pulse signal is input, on the basis of the output voltage (or any of a reference voltage, an output current and an output power). The plurality of switch elements include ones having small ON resistance and ones having small parasitic capacitance. The switch element selection circuit selects one of the two types of switch elements according to a result of comparison between the output voltage and a threshold voltage. Based on this, the power supply apparatus described in Japanese Patent No. 3438330 selectively uses the switch elements having small parasitic capacitance or those having small ON resistance and large parasitic capacitance, depending on the output voltage, to perform voltage conversion.
With decreasing the ON resistance of the switch element (i.e., with increasing the MOS size), steady power consumption (loss) for a load of the switch element is decreased, and therefore a high efficiency can be obtained. Whereas, with decreasing the ON resistance of the switch element (with increasing the MOS size), the parasitic capacitance is increased. For these reasons, a difference in a transition period of a signal level arises between cases of the large and small ON resistances of the switching element. If the transition period becomes longer, a switching loss (transient loss) becomes larger and therefore the efficiency is reduced in a case of a small output voltage. According to Japanese Patent No. 3438330, the switching regulator (power supply apparatus) of a variable output voltage type can efficiently perform a voltage conversion by switching to the switch element having the appropriate ON resistance with respect to each output voltage.
The inventor of the present application has recognized the following point.
According to the power supply apparatus described in Japanese Patent No. 3438330, a switch element (ON resistance value) is selected depending on a result of the comparison between a predetermined threshold voltage and the output voltage. That is, a switch element (ON resistance value) to be selected for every predetermined threshold voltage is fixed. The load current Il upon voltage conversion does not necessarily coincide with the load current Ides corresponding to the selected switch element. In such a case, the efficiency of the power supply apparatus comes to a value lower than the optimum value (efficiency ηD) as described above. The efficiency curve 70 shown in FIG. 3 also depends on values of a coil and a capacitor (e.g., the filter circuit 200 in FIG. 1) attached outside an IC chip, besides a characteristic (ON resistance value) of the switch element. For this reason, in a case where the switch element (ON resistance value) to be selected for every operating condition (threshold voltage) is fixed as in Japanese Patent No. 3438330, the outside parts should be replaced to perform the voltage conversion at the optimum efficiency ηD.